SOI Wafer
An SOI substrate is a type of wafer in which a SiO₂ layer is inserted between the Si substrate and the surface Si layer.Since it reduces parasitic capacitance in transistors, it is effective for improving operating speed and reducing power consumption.In conventional integrated circuits, isolation between devices is formed by reverse-biasing PN junctions. However, this generates parasitic diodes and stray capacitance with the substrate, causing signal delay and substrate leakage current.To reduce this stray capacitance, an insulating layer is formed beneath the MOSFET channel. This structure, which reduces stray capacitance, is called SOI.Moreover, a wafer containing such an insulating layer is called an SOI wafer. Conventional wafers are sometimes referred to as bulk silicon (or bulk wafers) to distinguish them from SOI wafers.
About ICEMOS TECHNOLOGY
- As the exclusive Japanese distributor of UK-based ICEMOS TECHNOLOGY Ltd., we provide services including SOI wafers, Si–Si bonding wafers, and processed SOI wafers (such as dielectric-isolated wafers), etc.
- ICEMOS TECHNOLOGY, formerly BCO Technology, has been offering world-class custom SOI solutions for more than ten years.
- We support our customers from small-volume prototyping for R&D to mass production.
About SOI Manufacturing Process
- There are two types of SOI wafer manufacturing process.
Process 1
Form buried oxide layer on handle layer and polish bonded device layer.
Process 2
Form buried oxide layer on device layer and polish bonded device layer.
About Customized SOI Wafer
We offer the specification based on customer's requirement.The following specifications are available.
- Device layer
- Thickness: The minimum thickness available is 1.5 µm.
- Buried Oxide
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- Direct oxidation to form the buried oxide layer is possible up to a thickness of 4 μm.
- More than 4um of oxide film are also available
ex) 5um (1um + 4um) Oxide film-Oxide film bonding
- Oxide film with a thickness of more than 4um
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For example, a 5um oxide layer (1um + 4um) can be used to form a buried oxide layer by bonding, however bonding oxide-to-oxide (SiO₂ + SiO₂) does not provide stronger bonding strength than bonding silicon to oxide (Si + SiO₂).
- Handle layer
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If you would like a handle layer with a thickness of less than 300 µm, we can offer polishing.
Ex) handle layer : 325µm -> polish to 150µm**Measured based on the total thickness of the SOI wafer. Processing with a target tolerance of ±2 µm is possible.
- Backside polishing of the handle layer
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We can offer backside polishing for the handle layer. The thickness will be measured based on the total thickness of the SOI wafer.
*Device layer polishing is also possible upon request.
- Field oxide and other film deposition processes
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- We offer field oxide film deposition on the surface of SOI wafers.
- Deposition of nitride films and metal films are also available.
- Bonding strength
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We can fabricate SOI wafers with reduced bonding strength between the device layer and the buried oxide layer.
*For wafers with standard bonding strength, past test data have shown that the bonding interface is not affected by etching in 48% HF for 70 minutes.
- SOI wafers with reduced bonding strength
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We can specially fabricate SOI wafers with reduced bonding strength at the bonding interface.
- Standard specifications of
ICEMOS TECHNOLOGY, LTD. -
Size: 4inch,5inch,6 inch,8inch
http://www.icemostech.com/soi-wafers.html
Product Overview of SOI Wafer Fabrication
Cavity-patterned wafer
We offer cavity processing of the BOX layer, handle layer, and other layers.
Patterned SOI wafer
Various patterning processes are available. The following types of patterning can be performed:
Product Overview of Dielectric Isolation Wafers
SOI wafer trench + refill process
Trench processing and polysilicon refill process on SOI wafers enable the fabrication of dielectrically isolated wafers.
Please refer to the link below for detailed specifications
http://www.icemostech.com/tsoi-wafers.html
Si-Si Bonding Wafer
By directly bonding two silicon wafers (e.g., a high-resistivity wafer and a low-resistivity wafer), it is possible to fabricate wafers that can serve as an alternative to epitaxial wafers.A key feature is that, since the wafers are bonded directly, auto-doping at the wafer interface is less likely to occur.Depending on the thickness, this method can reduce costs compared to growing a thick epitaxial layer. The fabrication process involves bonding two silicon wafers and then polishing the device layer to the desired thickness. Si–Si bonding wafers (Si–Si bonded wafers) have proven to be a cost-effective alternative to thick epitaxial layers traditionally used in applications such as power devices and PIN diodes.
About SOI Wafer Stock Sales
Overseas stock from ICEMOS TECHNOLOGY is also available. Please contact us for detailed specifications or inquiries.The most up-to-date stock list can be provided upon request.